Hello, World! I'm
Abdelrahman Fouda
Senior Nanotechnology & Nanoelectronics Engineering student at Zewail City — specializing in VLSI, ASIC/FPGA design, RISC-V, and embedded systems.
01. aboutAbout Me
I'm a senior Nanotechnology & Nanoelectronics Engineering student at Zewail City of Science and Technology, specializing in VLSI, Digital & Analog design, RISC-V, ASIC/FPGA, and semiconductor fabrication.
My interests span embedded systems, robotics, RF & mixed-signal ICs, optical communication, and integrated silicon photonics — bridging nanoscale physics with real-world hardware.
My graduation project focuses on “RISC-V Integration and ISA Extension for Efficient MSM on BLS12-377 and BLS12-381 Curves” — hardware acceleration for zero-knowledge proof cryptography.
6th October, Egypt
abdofouda9955@gmail.com
+20 01018730480
Arabic (native), English (B2/C1)
3.01
GPA
15+
Projects
2026
Grad Year
2
Languages
02. skillsTechnologies & Tools
HDLs & Digital Design
EDA & CAD Tools
Programming Languages
Photonics & RF
Embedded & Robotics
Fabrication & Characterization
3D Design & PCB
03. experienceExperience & Education
Work Experience
Robotics & Tiny ML Engineering Trainee
Zewail City of Science and Technology
Jul 2024 – Oct 2024 | 6th October, Egypt
- ▸Designed and built an obstacle avoidance robot using Raspberry Pi Pico and radar sensors.
- ▸Trained and deployed a quantized TensorFlow Lite model achieving 83.9% accuracy on hardware.
- ▸Transitioned Python-based models into C arrays for embedded system deployment.
- ▸Utilized Q-learning for data collection and neural network training.
- ▸Validated robot performance through real-world testing and simulation.
Education
B.Sc. Nanotechnology & Nanoelectronics Engineering
University of Science and Technology, Zewail City
Oct 2020 – Present
GPA: 3.01 / 4.0
Thesis
“RISC-V Integration and ISA Extension for Efficient MSM on BLS12-377 and BLS12-381 Curves”
Relevant Courses
04. projectsSelected Projects
RISC-V ISA Extension for MSM
Graduation project: hardware acceleration for zero-knowledge proof cryptography via RISC-V ISA extension targeting efficient Multi-Scalar Multiplication on BLS12-377 and BLS12-381 elliptic curves.
ASIC & FPGA Flow Comparison
Implemented RTL design using full ASIC flow (Synopsys DC + ICC + PT) with NangateOpenCell 45nm PDK and FPGA flow on Spartan 6. Evaluated frequency, power, area, and utilization metrics.
Obstacle Avoidance Robot + TinyML
Built obstacle avoidance robot on Raspberry Pi Pico with radar sensors. Deployed quantized TensorFlow Lite model achieving 83.9% hardware accuracy, trained via Q-learning.
32×12-bit 6T SRAM at 65nm
Full-custom design and analysis of a 32×12-bit SRAM in Cadence Virtuoso. Schematic, layout, DRC/LVS, and test benches. Read/write delay and power consumption optimization.
Two-Stage CMOS Op-Amp
Designed a two-stage CMOS operational amplifier in Cadence Virtuoso at 65nm — targeting gain, GBW, phase margin, and CMRR specifications.
CMOS Transistor Fabrication Design
250nm CMOS transistor fabrication process design: oxidation, photolithography, deposition, etching, and ion implantation calculations. Simulated with SILVACO TCAD.
Self-Balancing Robot
Microcontroller-based robot using IMU (accelerometer + gyroscope) sensor fusion and PID control algorithms to maintain dynamic balance via motor driver feedback.
FM Communication System
Designed and implemented a complete FM communication system (modulation, channel, demodulation) using MATLAB and LabVIEW with real-time signal analysis.
4-bit ALU with PCB
Full-stack 4-bit ALU: circuit design, PCB layout in EasyEDA, breadboard prototype with 74xx ICs, and SystemVerilog functional verification.
Photonic Crystal Fiber Simulation
Designed PCF structure, performed eigenmode/dispersion simulations, and analyzed guiding properties including confinement loss and effective mode area.
Security System (FreeRTOS)
Multi-sensor security system using motion and sound sensors integrated on Tiva C Series (TM4C123) with FreeRTOS task scheduling and real-time response.
SAP1 Architecture
Designed and implemented the Simple As Possible 1 (SAP-1) CPU architecture in Logisim, followed by full hardware implementation using discrete logic ICs.
05. contactGet In Touch
I'm currently open to new opportunities in VLSI, embedded systems, or research roles. Whether you have a question or just want to connect — my inbox is always open.
abdofouda9955@gmail.com
/in/abdelrahman-fouda
GitHub
abdelrahman-fouda
+20 155 175 2962