// booting identity_module.v
Abdelrahman Fouda
Vpp 140.0 mV
Vrms 48.2 mV
Electronics Engineering graduate (Zewail City, 2025) · MSc student at the University of Bologna. Designing from the transistor up — VLSI, ASIC / FPGA, RISC-V, embedded systems & silicon photonics.
About Me
Technologies & Tools
HDLs & Digital Design
EDA & CAD Tools
Programming Languages
Photonics & RF
Embedded & Robotics
Fabrication & Characterization
3D Design & PCB
Experience & Education
<WORK_EXPERIENCE />
Co-Founder
→ KIDVITY · Egypt- ▸Co-founded an educational-toy startup focused on STEM projects for children.
- ▸Led product design, basic prototyping, and iteration on learning value.
- ▸Handled planning, teamwork, and technical communication for non-technical audiences.
Robotics & Tiny-ML Engineering Trainee
→ Zewail City of Science and Technology
- ▸Built an obstacle-avoidance robot on Raspberry Pi Pico with radar sensors.
- ▸Deployed a quantized TF-Lite model — 83.9% on-hardware accuracy.
- ▸Ported Python models to C arrays for embedded deployment.
- ▸Used Q-learning for data collection + training.
- ▸Validated performance via real-world testing and simulation.
<EDUCATION />
MSc Electronic Engineering (LM-29)
→ University of Bologna · Alma Mater StudiorumField: Electronics & Automation · EQF Level 7 · Bologna, Italy
BSc Nanotechnology & Nanoelectronics Engineering
→ University of Science and Technology, Zewail CityGPA: 3.05 / 4.0 · Giza, Egypt
// thesis
“RISC-V Integration and ISA Extension for Efficient MSM on BLS12-377 and BLS12-381 Curves”
// relevant_courses[12]
Selected Projects
RISC-V ISA Extension for MSM
Graduation project: hardware acceleration for zero-knowledge proof cryptography via a RISC-V ISA extension targeting efficient Multi-Scalar Multiplication on BLS12-377 and BLS12-381 elliptic curves.
ASIC & FPGA Flow Comparison
RTL design implemented through full ASIC flow (Synopsys DC + ICC + PT) with NangateOpenCell 45 nm PDK and FPGA flow on Spartan 6. Evaluated frequency, power, area, and utilization.
Obstacle Avoidance Robot + TinyML
Obstacle-avoidance robot on Raspberry Pi Pico with radar sensors. Deployed a quantized TensorFlow Lite model — 83.9% on-hardware accuracy — trained via Q-learning.
32×12-bit 6T SRAM at 65 nm
Full-custom design of a 32×12-bit SRAM in Cadence Virtuoso. Schematic, layout, DRC/LVS, and testbenches. Read/write delay and power consumption optimized.
Two-Stage CMOS Op-Amp
Designed a two-stage CMOS operational amplifier in Cadence Virtuoso at 65 nm — targeting gain, GBW, phase margin, and CMRR specifications.
CMOS Transistor Fabrication Design
250 nm CMOS transistor process design: oxidation, photolithography, deposition, etching, and ion implantation calculations. Simulated in SILVACO TCAD.
Self-Balancing Robot
Microcontroller-based robot using IMU (accelerometer + gyroscope) sensor fusion and PID control to maintain dynamic balance via motor-driver feedback.
FM Communication System
Complete FM communication system (modulation, channel, demodulation) in MATLAB and LabVIEW with real-time signal analysis.
4-bit ALU with PCB
Full-stack 4-bit ALU: circuit design, PCB layout in EasyEDA, breadboard prototype with 74xx ICs, and SystemVerilog functional verification.
Photonic Crystal Fiber Simulation
Designed a PCF structure, ran eigenmode / dispersion simulations, and analyzed guiding properties including confinement loss and effective mode area.
Security System (FreeRTOS)
Multi-sensor security system using motion + sound sensors on Tiva C (TM4C123) with FreeRTOS task scheduling and real-time response.
SAP-1 Architecture
Simple-As-Possible-1 CPU architecture in Logisim, followed by full hardware implementation using discrete logic ICs.
Get In Touch
MSc student at the University of Bologna — open to research collaborations, internships, and opportunities in VLSI, embedded systems, and electronic engineering. Inbox always open.
abdofouda9955@gmail.com
/in/abdelrahman-m-fouda
GITHUB
abdelrahman-fouda
+20 155 175 2962